Polysilicon thin-film transistors (poly-Si TFTs) have attracted much attention for use in active-matrix liquid-crystal displays (LCDs) since they can be integrated with peripheral driving circuits because of their high effect mobility and driving current. In order to simplify process complexity and lower cost, previous studies have proposed a system-on-panel (SOP) display technology with high-performance poly-Si TFTs designed as functional devices on an LCD panel as controller and memory. SOP technology is primarily focused on portable electronics; thus, low power consumption is required to ensure long battery life. As is well known, nonvolatile memory is widely utilized for data storage in various portable electronics due to its advantages of low power consumption and nonvolatility.
According to the basic operation principle of memory device, a gate read voltage Vread between the threshold voltages of program operation and erase operation is applied to the gate in order to measure the corresponding current and identify the status “0” or “1” of the memory device. However, several studies have reported that a high gate-induced drain leakage (GIDL) current could cause misidentification of that status in silicon-oxide-nitride-oxide-silicon (SONOS) memory device because some carriers generated from GIDL would flow to a Si substrate and result in threshold voltage disturbance (Vt disturbance) and the large GIDL current would cause read error in memory array. Therefore, for SONOS TFTs, this problem will be more serious due to the significant trap-assisted GIDL current. In addition, the leakage current also causes high power consumption.
The conventional structure of the lightly-doped drain (LDD) can be used to reduce the effect caused by the leakage current. However, the production cost is increased due to the additional processing step. Therefore, a method used to enhance the interpretation about the status of the memory device without increasing the additional production cost is needed.